Hitachi 6309 Description

Description of Additional Registers

The 6309 has 7 additional registers. Only 4 of these are actual registers. 2 are combinations of registers, and the last is a constant-value register. These registers are:

  • ACCE: 8 bit accumulator.
  • ACCF: 8 bit accumulator.
  • W: 16 bit concatenated register (ACCE and ACCF combined).
  • Q: 32 bit concatenated register (ACCA, ACCB ,ACCE and ACCF combined).
  • V: 16 bit register (which can only be accessed with the inter-register instructions).
  • 0: zero register
  • MD: 8 bit mode/error register.

ACCE and ACCF both work in much the same manner as the ACCA and ACCB accumulators. This makes for easier programming in math and data oriented routines.

The W register is like the D register in the 6809. It is a concatenated register containing the values of ACCE and ACCF as one 16 bit value. ACCE is contained in the high 8 bits and ACCF is contained in the low 8 bits.

The Q register is a 32 bit concatenated register. This register is composed of the concatenation of D and W, which in turn are composed of the registers ACCA, ACCB, ACCE and ACCF respectively. This register is used mostly with the additional math instructions supplied with the 6309 which will be discussed later.

The V register is a 16 bit register that can only be accessed with inter-register instructions such a TFR and EXG. The contents of this register will not change if the CPU is reset, allowing this register to be used as a constant value for the program.

The 0 register is always zero, independant of writes to it. It enables a zero value to be used in inter-register operations without accessing memory, or changing the value of another register.

The MD register is a mode and error register and works much in the same way as the CC register. The bit definitions are as follows:

Write bits

  • Bit 0 - Execution mode of the 6309.
    • If clear ( 0 ), the cpu is in 6809 emulation mode.
    • If set ( 1 ), the cpu is in 6309 native mode.
  • Bit 1 - FIRQ mode
    • If clear ( 0 ), the FIRQ will occur normally.
    • If set ( 1 ) , the FIRQ will operate the same as the IRQ
  • Bits 2 to 5 are unused

Read bits - One of these bits is set when the 6309 traps an error

  • Bit 6 - This bit is set ( 1 ) if an illegal instruction is encountered
  • Bit 7 - This bit is set ( 1 ) if a zero division occurs.

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