Hitachi 6309 Description

Inter-Register Instructions

The new Inter-Register instructions (ADCR, ADDR, CMPR, EORR, ORR, SBCR, and SUBR) all work the same as their register/memory (ADCA, ADDA, etc.) counterparts except that they operate between registers. All of the new instructions use the same post-byte information as the normal TFR instruction and use the format of R0,R1 (register 0 and Register 1 respectively) with the result going into R1. See Block Transfers for information on the TFR block move instructions.

Mixed-size inter-register operations default to using identical sized register. So TFR A,X actually executes as TFR D,X. You could also do 'lea(d) d,pc' calculations by doing 'addr pc,d'. As the new inter-register instructions can now perform math using the PC register, REALLY odd possibilities exist. Try looking at code like 'eorr d,pc', and figuring out where it ends up.

Inter-register instructions with 16-bit r1 and CC or DP (8-bit r2) are legal, but the results are unknown.

Bit Manipulation of Memory Locations

The AIM, EIM, OIM and TIM instructions all do logical bit manipulations to locations in memory, with the result stored into the location, and the respective bits for each instruction set in the CC register. They can be used in the DIRECT, INDEXED or EXTENDED adressing modes.

Instruction descriptions:

  • AIM - AND IN MEMORY
  • EIM - EOR IN MEMORY
  • OIM - OR IN MEMORY
  • TIM - TEST bits IN MEMORY

Instruction format:

X, post byte, operand

Where X is the instruction op-code, post-byte contains the bits to AND, OR, EOR or TEST against the memory location, and the operand is the memory location or indexing post-byte depending on the mode of operation.

Mnemonic format:

Instruction logical operation value, memory location or index operation

Mnemonic example:

AIM #$0F,$E00

The example takes the contents of memory location $E00, does a LOGICAL and with the Value #$0F and then stores the result back into $E00.

Bit Transfers Between Memory Locations and Registers

The BAND, BIAND, BOR, BIOR, BEOR, BIEOR, LDBT, and STBT all do logical operations to bits for the n-th bit in a memory location and the m-th bit of a register. The LDBT and STBT instructions allow you to transfer certain bits between registers and memory locations. All instructions allow you to specify which register to use, which bit location to use in the register, which bit location to use in the memory location, and the memory location to use. This allows you to transfer/or do a logical operation with the 7th bit of a register and the 3rd bit of a memory location. All bits are accessible on either the register or memory locations. The only limitations are that the instructions can only be used with the A and B accumulators and the CC (condition Code) registers. It should also be noted that these instructions can only be used in the DIRECT addressing mode.

Instruction description:

  • BAND - AND a bit in a register with bit from memory location
  • BIAND - AND a bit in a register with the complement of the bit in memory
  • BOR - OR a bit in a register with a bit from a memory location
  • BIOR - OR a bit in a register with the complement of the bit in memory
  • BEOR - EOR a bit in a register with a bit from a memory location
  • BIEOR - EOR a bit in a register with the complement of the bit in memory
  • LDBT - Load a bit from a memory location into a bit in a register
  • STBT - Store a bit from a register into a memory location.

Instruction format:

X post-byte, memory location

Where X is the instruction op-code, the post-byte contains the register, source and destination bit information and the memory location is the 8 bit value of the memory location to be used (Remember only DIRECT mode is allowed with these instructions).

Mnemonic format:

instruction, register, source bit, destination bit, memory location

Mnemonic example:

BOR A,1,7,$00

The example would take the first (1) bit of register A (A) and OR it into the 7th (7) bit of memory location $00 ($00) of the direct page (DP register value)

The post-byte of these instructions are not the same as the post-byte used in any other operation (indexed or inter-register) as all of the information (register, source and destination bit) is contained in one post-byte value.

Block Transfers

Block transfers are used to move a certain number of bytes from one place in memory to another with the use of one instruction. Two 16 bit registers (X, Y, U or S) are used to specify the source and destination addresses, and the size of the block to be transferred is specified with the W register. It should be noted that even though the IRQ and FIRQ only occur after the current instruction is finished, block moves can be interrupted. After the interrupt returns, the last byte read is read once more. i.e. It is read _twice_ by the CPU This can cause problems with memory mapped I/O devices, so caution is advised when using the block transfers. There isn't much control over these 4 instructions so the only thing applicable for them would be large block moves such as scrolling the screen or clearing an area in memory with a certain value.

TFM r0+,r1 and TFM r0,r1+ can be considered a poor mans DMA channel. Since all the data is either copied into or read from one memory location.

Four types of block transfers have been provided.

Mnemonic examples:

(R0 - source address register, R1 - destination address register.)

  • TFM r0+,r1+ - Transfer from R0 to R1 in incrementing order.
  • TFM r0-,r1 - Transfer from R0 to R1 in decrementing order.
  • TFM r0+,r1 - Pour from R0 into R1, only incrementing R0 (R1 stays the same).
  • TFM r0,r1+ - Read from R0 into R1, only incrementing R0 (R1 stays the same).

Mnemonic example:

   LDW #$100
   LDX #$600
   LDY #$700
   TFM X+,Y+

The example would move 256 (LDW #$0100) bytes from #$600 (LDX #$0600) in memory to #$700 (LDY #$0700) in memory, incrementing the value of each register (X and Y), and decrementing the value of the W register each time a byte if moved.

When moves like this are done, the pointer registers (X and Y in the example) will not be the same value they were before the transfer was initiated, but will but will be their original values PLUS the value of the W register (#$100 in the example). So in the example once the move is complete, the value of X will be returned as #$700 and the value of Y will be returned as #$800. The value of W register will be 0.

It is illegal to use any of the CC, DP, W, V, 0, or PC registers as either a source or destination register. Note that the D register CAN be used with the TFM instructions.

New math commands

The 6309 has 3 additional math instructions. A 16 bit by 16 bit signed multiply (MULD), a 16 bit by 8 bit signed divide (DIVD) and a 32 bit by 16 bit signed divide (DIVQ). These instructions can all be used in Immediate, direct, indexed and extended addressing modes.

The MULD (16 bit by 16 bit) instruction does a signed multiply of the contents of the D register and a value from memory (or in direct mode). The signed result is stored in the Q register.

The DIVD (16 bit by 8 bit) instruction does a signed divide of the contents of the D register with a value from memory (or in direct mode). The signed result is stored with the quotient in W and the modulo (remainder) in D.

The DIVQ (32 bit by 16 bit) instruction does a signed divide of the contents of the Q register with a value from memory (or in direct mode). The signed result is stored with the quotient in W and the modulo (remainder) in D.

Error Trapping

The 6309 has an internal error trapping handler that will jump to a specific location in memory when either an error is encountered in the DIVision instructions (only divide by zero) or an illegal instruction is encountered. When an error is encountered, the 6309 will jump to the memory location contained in $FFF0 (and $FFF1) which was originally reserved by the 6809.

The trap may cause problems with machines that have $FF00 hardcoded with the values $0000. A new EPROM should be burned to correct for the new behaviour of the 6309.

As many people know, an illegal instruction trap is extremely useful for debugging programs, as it prevents the entire machine from crashing when a bug is encountered.

Note that many pseudo-legal instructions on the 6809 are now illegal on the 6309, e.g. $1020xxxx executes as an LBRA on a 6809, but results in a trap on a 6309.

Additional Instructions

The 6309 has MANY new instructions. Most are variations of old instructions of the 6809 for use with the new registers. The new instruction set can be used in both native and emulation mode. Here is a list of the new instructions of the 6309:

  • ADCD - Adds immediate or memory operand to the D register plus the current status of the carry with the result going to D.
  • ADCR - Adds two registers together plus the current status of the carry.
  • ADDE, ADDF, ADDW - Add of immediate or memory operand to E, F or W with results going to E, F or W
  • ADDR - Adds two registers together
  • ANDD - Logical AND of immediate or memory operand to D register with result going to D.
  • ANDR - Logical AND of a register with the contents of another register
  • ASLD (Same as LSLD) - Arithmetic shift left. Shifts D one bit left, clearing LSB.
  • ASRD - Arithmetic shift right of the D register with sign extending.
  • BITD - Test any bit or bits of the D register.
  • BITMD - Test any bit or bits of the MD (mode) register.
  • CLRD, CLRE, CLRF, CLRW - Clear register D, E, F or W to zero.
  • CMPE, CMPF, CMPW - Compares the contents of E, F or W with the immediate or memory operand. Sets all CC except H on result.
  • CMPR - Compares one register to another and sets all CC bits except H on result.
  • COMD, COME, COMF, COMW - One's complement D ,E, F, or W. Changes all zero's to one's and all one's to zero's.
  • DECD, DECE, DECF, DECW - Decrement D, E, F, or W by 1.
  • DIVD, DIVQ - Does a 16 bit by 8 bit (DIVD) or a 32 bit by 16 bit (DIVQ) signed divide with immediate or memory operand with quotient in W and modulo (remainder) in D.
  • EORD - Logical exclusive OR of D and immediate or memory operand.
  • EORR - Logical exclusive OR of one register with the value of another register.
  • INCD, INCE, INCF, INCW - Increment D, E, F or W by 1.
  • LDE, LDF, LDQ, LDW, LDMD - Standard loading of E, F, Q, W or MD with immediate data value or operand from memory. (LDMD only valid with IMMEDIATE mode)
  • LSLD (Same as ASLD) - Logical shift left. Shifts D one bit left, clearing LSB.
  • LSRD, LSRW - Logical shift right. Shifts D or W one bit right, clearing MSB.
  • MULD - Performs as 16bit by 16bit signed multiply with immediate or operand from memory. Result stored in Q.
  • NEGD - Two's complement D register.
  • ORD - Logical OR of register D and immediate or memory operand.
  • ORR - Logical OR of one register with another.
  • PSHSW, PSHUW - Stores contents of the W register on the (system or user) stack.
  • PULSW, PULUW - Pull value from (system or user) stack into register W.
  • ROLD, ROLW - Rotate D or W one bit left through the Carry Condition code.
  • RORD, RORW - Rotate D or W one bit right through the Carry Condition code.
  • SBCD - Subtract an immediate or memory operand plus any borrow in Carry from contents of D. Result stored in D.
  • SBCR - Subtract the value of one register from another plus any borrow in the CC carry.
  • SEXW - sign exdend the W register into the D register.
  • STE, STF, STQ, STW - Store register E, F, Q or W to memory location (E,F), two memory locations(W), or four memory locations (Q).
  • SUBE, SUBF, SUBW - Subtract immediate or memory operand from E, F or W. Result stored back in same register.
  • SUBR - Subtract the value of one register from another.
  • TFM (Block transfer) - Transfer W number of bytes from one location to another. Returns pointer registers offset of the starting value in the W register and returns the W register as 0. Indexed operation only
  • TSTD, TSTE, TSTF, TSTW - Test contents of D, E, F or W by setting N and X condition codes based on data in register.

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