68HC11 Introduction

        .cr     68hc11      To load this cross overlay

The Motorola 68HC11 family of micro controllers is a powerful addition to the 6805 family. The most important enhancements are two 16-bit index registers with their associated addressing modes, EEPROM memory and power savings capabilities. This processor is also equipped with a direct page addressing mode, like in most other Motorola processor families.
A large number of models exist with an ever increasing number of peripherals and other on board facilities.

Programming Model

The programming model in the picture below shows the most important registers of the 68HC11 controller. I only include a little summary about the features of the 68HC11's programming model here. It is not my intention to make the original documentation obsolete, so please refer to the original documentation for further details.

The 68HC11 has a very powerful addressing mode called direct page addressing, which is also called zero page addressing. This way all 256 bytes of the first page in memory can be addressed with only 8 bits. These 256 addresses can be considered the "registers" of the 68HC11!

The Accumulators A and B

The 68HC11 is equipped with two 8-bit accumulators. Both Accumulators are technically the same and can both be used for a variety of arithmetic operations.
Both Accumulators can be concatenated to form a 16-bit accumulator, called D. Accumulator A becomes the most significant byte of the double accumulator.

The Condition Code Register

The CC register holds all the system flags. Most of the flags reflect the status of the machine after mathematical or logical instructions. Other flags are set or cleared under program control.

The CC register contains 8 system flags:

Bit 7	S	Stop disable Flag
Bit 6	X	XIRQ mask Flag
Bit 5	H	Half Carry Flag
Bit 4	I	IRQ Flag
Bit 3	N	Negative sign Flag
Bit 2	Z	Zero Flag
Bit 1	V	Overflow Flag
Bit 0	C	Carry Flag

IRQ interrupts are disabled when the I bit is set.
XIRQ interrupts are disabled after reset, until the X bit is cleared by software. From then on the X bit can only be set by hardware during an XIRQ. Clearing is done by software only by using the TAP or RTI instructions.

The Index registers X and Y

Both index registers can be used to indirectly point to data in memory. The X and Y registers are identical to each other.
Instructions that use the Y register are often one byte longer and use one extra machine cycle than if the X register was used instead.

The Stack Pointer SP

The 68HC11 is equipped with a 16-bit stack pointer. This means that the stack can be placed anywhere in RAM memory. The stack grows down in memory when data is pushed on to it.

The stack pointer SP always points to the next free location on the stack. When a byte is pushed on to the stack the data is stored in memory first, then the stack pointer is decremented. The LSB of a 16-bit register is saved first during a push instruction.

Subroutine calls will save the address of the instruction following the JSR or BSR instruction on to the stack. The RTS instruction simply pulls the PC from the stack, effectively continuing directly after the JSR or BSR instruction.

Interrupts will push the PC on the stack and all processor registers. The order in which all data is pushed is shown below:

  PCL, PCH, IYL, IYH, IXL, IXH, A, B, CCR

It goes without saying that the pull order is just the other way around!

Please note that it is very strange that the Accu A is stacked prior to Accu B. Normal stacking occurs with LSB first, so I would have expect that Accu B was stacked first being the LSB of Accu D.

The Program Counter

The program counter PC is normally incremented after fetching each instruction or operand byte during program execution. The only way you can change this behaviour is with the jump, subroutine and return instructions. Also interrupts can change the program counter's value.

Timing

SB-Assembler Version 3 can show you the cycle times of each instruction when the TON list flag is switched on. The numbers presented are the number of clock pulses the processor needs to execute the instruction.

Reserved Words

The SB-Assembler 68HC11 cross overlay has only two reserved words. It is not very likely though that you will run into trouble if you use any of the reserved words as label names. But it is always better to be safe than sorry, so why use them when you have so many alternatives to choose from.

The reserved words are: X, Y.

Special Features

Indexed addressing modes

The official notation of the indexed addressing mode is offset,X, where offset is an unsigned 8-bit constant value. Usually the offset value is $00 and that can be written in three different ways in the SB-Assembler:

        LDAA   $00,X
        LDAA   ,X
        LDAA   X

All three instructions have the same effect and all use an offset value of $00.

Forced direct page and extended addressing modes

Direct page addressing mode is also called zero page addressing mode because it always uses the first 256 bytes of memory space.
With direct addressing mode you specify a memory location that can be addressed with only one byte (instead of 2 for all other memory locations). This way the 68HC11 can be seen as a micro processor with 256 registers.

The SB-Assembler automatically selects direct addressing mode when that mode is available and the high byte of the address is zero.
We only know for sure that the high byte of the address is zero if there was no unresolved label used in the expression identifying the address. If a forward referenced label is used in an address expression we automatically assume the worst case situation and opt for extended addressing mode (2 bytes address field).

You may override this automatic selection of addressing mode by preceding the address field with a < or a > symbol.
The < symbol forces the assembler to use direct page addressing mode, even if the address expression contains a forward referenced label.
On the other hand the > symbol will force the assembler to use the extended addressing mode, even if the address could be resolved to a direct address.
A Out of range error will be reported if you try to force to use the direct addressing mode where the high byte of the address isn't zero.

Examples:

0010-           LABEL     .EQ    $10           A direct page address
8000-96 10                LDAA   LABEL         Appears to be direct page
8002-96 11                LDAA   <FORWARD      Clearly a forward referenced label
8004-97 12                STAA   $12           Is a direct page address
8006-B7 00 11             STAA   >$11          Force extended addressing mode
0011-           FORWARD   .EQ    $11           A direct page address 

Small difference in bit addressing notation

The bit addressing notation on the SB-Assembler differs slightly from the original Motorola notation. This is because the SB-Assembler won't allow spaces in operand fields, while Motorola recommends them at that point.

All differences apply only to the bit mask operand. With the Motorola assembler the bit mask (and the branch destination address) is preceded by a space character.
The SB-Assembler won't allow that and requires you to use a comma instead. You may also use any of the immediate prefixes in front of the bit mask, something that is officially not required.

Examples:

        BSET    $12,%0001.1000     Almost the same as Motorola ;-)
        BSET    0,X,#%0001.1000    The most obvious notation
        BSET    ,X,#%0001.1000     0 offset may also be like this
        BSET    X,#%0001.1000       or like this
        BSET    0,X,%0001.1000     No immediate prefix here

Please note that the comma in front of all the bit masks would have been a space with the Motorola assembler.

Extra instructions

I have added some mnemonics to the 68HC11 cross assembler, all concerning Accu D operations. Normally the assembler isn't supposed to understand these instructions, but I have added them here for your convenience. If you don't like them, simply don't use them.
These compound instructions are all composed of 2 separate instructions. Please note that such a compound statement doesn't always leave the system flags in the expected state!

Accumulator D compound instructions

New	Native	Description
CLRD	CLRA CLRB	Clear D
COMD	COMA COMB	Complement D
ROLD	ROLB ROLA	Roll left D
RORD	RORA RORB	Roll right D
PSHD	PSHB PSHA	Push Accu D on the stack
PULD	PULA PULB	Pull Accu D from the stack

Apart from the table above you can also use the short instruction form LDA instead of LDAA, or STB instead of STAB, etc.

Overlay Initialization

Two things are set while initializing the 68HC11 overlay every time it is loaded by the .CR directive.

• Big endian model is selected for 16-bit addresses and for the .DA and .DL directives. This means that words or long words are stored with their high byte first.
• The maximum program counter value is set to $FFFF.

Differences Between Other Assemblers

There are some differences between the SB-Assembler and other assemblers for the 68HC11 processor. These differences require you to adapt existing source files before they can be assembled by the SB-Assembler. This is not too difficult though, and is the (small) price you have to pay for having a very universal cross assembler.

• Not all assemblers will understand all the compound instructions.
• The already mentioned difference in bit addressing notation.
• Not all assemblers will understand forced direct page and extended addressing modes.
• The obvious differences in notation of directives and radixes common to all SB-Assembler crosses.
• Don't forget that the SB-Assembler does not allow spaces in or between operands. Only Version 3 will allow one space after each comma separating operands in the operand field.